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1 file number 2803.4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 407-727-9207 | copyright intersil corporation 1999 hmu16, hmu17 16 x 16-bit cmos parallel multipliers the hmu16 and hmu17 are high speed, low power cmos 16-bit x 16-bit multipliers ideal for fast, real time digital signal processing applications. the x and y operands along with their mode controls (tcx and tcy) have 17-bit input registers. the mode controls independently specify the operands as either twos complement or unsigned magnitude format, thereby allowing mixed mode multiplication operations. two 16-bit output registers are provided to hold the most and least signi?ant halves of the result (msp and lsp). for asynchronous output, these registers may be made transparent through the use of the feedthrough control (ft). additional inputs are provided for format adjustment and rounding. the format adjust control (fa) allows the user to select either a left shifted 31-bit product or a full 32-bit product, whereas the round control (rnd) provides the capability of rounding the most signi?ant portion of the result. the hmu16 has independent clocks (clkx, clky, clkl, clkm) associated with each of these registers to maximize throughput and simplify bus interfacing. the hmu17 has only a single clock input (clk), but makes use of three register enables ( enx, eny and enp). the enx and eny inputs control the x and y input registers, while enp controls both the msp and lsp output registers. this con?uration facilitates the use of the hmu17 for microprogrammed systems. the two halves of the product may be routed to a single 16-bit three-state output port via a multiplexer, and in addition, the lsp is connected to the y-input port through a separate three-state buffer. features 16 x 16-bit parallel multiplier with full 32-bit product high-speed (35ns) clocked multiply time low power operation -i ccsb = 500 a maximum -i ccop = 7.0ma maximum at 1mhz supports twos complement, unsigned magnitude and mixed mode multiplication hmu16 is compatible with the am29516, lmu16, idt7216 and the cy7c516 hmu17 is compatible with the am29517, lmu17, idt7217 and the cy7c517 ttl compatible inputs/outputs three-state outputs applications fast fourier transform analysis digital filtering graphic display systems image processing radar and sonar speech synthesis and recognition ordering information part number temp. range ( o c) package pkg. no. hmu16jc-35 0 to 70 68 ld plcc n68.95 HMU16JC-45 0 to 70 68 ld plcc n68.95 hmu16gc-35 0 to 70 68 ld cpga g68.b hmu16gc-45 0 to 70 68 ld cpga g68.b hmu17jc-35 0 to 70 68 ld plcc n68.95 hmu17jc-45 0 to 70 68 ld plcc n68.95 hmu17gc-35 0 to 70 68 ld cpga g68.b hmu17gc-45 0 to 70 68 ld cpga g68.b data sheet november 1999
2 pinouts 68 lead plcc top view 68 lead cpga top view 6867666564636261 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 18 19 20 21 22 23 24 25 26 27282930313233 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 p15, p31 nc p13, p29 p12, p28 p11, p27 p10, p26 p9, p25 p8, p24 p7, p23 p6, p22 p5, p21 p4, p20 p3, p19 p2, p18 p1, p17 p0, p16 nc fa ft mspsel gnd gnd v cc v cc tcy tcx rnd clkx ( enx) x15 x14 x13 nc oep x11 y15, p15 y14, p14 y13, p13 y12, p12 y11, p11 y10, p10 y9, p9 y8, p8 y7, p7 y6, p6 y5, p5 y4, p4 y3, p3 y2, p2 y1, p1 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 oel clkl (clk) clky ( eny) nc y0, p0 p14, p30 clkm ( enp) x12 11 10 9 8 7 6 5 4 3 2 1 n/c x12 x10 x8 x6 x4 x2 x0 clkl y0/p0 y1/p1 x11 x9 x7 x5 x3 x1 oel clky n/c oep clkm p30/ p28/ p26/ p24/ p22/ p20/ p18/ p16/ n/c n/c p31/ p29/ p27/ p25/ p23/ p21/ p19/ p17/ x13 x14 y2/p2 y3/p3 x15 clkx y4/p4 y5/p5 rnd tcx y6/p6 y7/p7 tcy v cc y8/p8 y9/p9 v cc gnd y10/ y11/ gnd msp y12/ y13/ ft f a y14/ y15/ b a kl cd e f gh j p10 p12 p14 p11 p13 p15 ( eny) (clk) ( enx) sel ( enp) p14 p15 p12 p13 p10 p11 p8 p9 p6 p7 p5 p3 p1 p0 p2 p4 hmu16, hmu17
3 functional block diagrams hmu16 hmu17 x0 - 15 tcx clkx register register rnd tcy y0 - 15/po - 15 register multiplier array format adjust msp resister lsp resister multiplexer oel clky f a ft clkm clkl mspsel oep p16 - 31/po - 15 x0 - 15 register register tcx tcx rnd tcy y0 - 15/po - 15 clk register multiplier array msp resister lsp resister format adjust oel multiplexer p16 - 31/po - 15 enx eny fa ft enp mspsel oep hmu16, hmu17
4 pin description symbol plcc pin number type description v cc 1, 68 v cc . the +5v power supply pins. a 0.1 f capacitor between the v cc and gnd pins is recommended. gnd 2, 3 gnd. the device ground. x0-x15 47-59, 61-63 i x-input data. these 16 data inputs provide the multiplicand which may be in two's complement or unsigned magnitude format. y0-y15/ p0-p15 27-42 i/o y-input/lsp output data. this 16-bit port is used to provide the multiplier which may be in two's complement or unsigned magnitude format. it may also be used for output of the least significant product (lsp). p16-p31/ p0-p15 10-25 o output data. this 16-bit port may provide either the msp (p16-31) or the lsp (p0-15). tcy, tcx 66, 67 i two's complement control. input data is interpreted as two's complement when this control is high. a low indicates the data is to be interpreted as unsigned magnitude format. ft 5 i feed through control. when this control is high, both the msp and lsp registers are transparent. when low, the registers are latched by their associated clock signals. f a 6 i format adjust control. a full 32-bit product is selected when this control line is high. a low on this control line selects a left shifted 31-bit product with the sign bit replicated in the lsp. this control is normally high, except for certain two's complement integer and fractional applications. rnd 65 i round control. when this control is high, a one is added to the most significant bit (msb) of the lsp. this position is dependent on the f a control; f a = high indicates rnd adds to the 2-15 bit (p15), and f a = low indicates rnd adds to the 2 -16 bit (p14). mspsel 4 i output multiplexer control. when this control is low, the msp is available for output at the dedicated output port, and the lsp is available at the y-input/lsp output port. when mspsel is high, the lsp is available at both ports and the msp is not available for output. oel 46 i y-in/p0-15 output port three-state control. when oel is high, the output drivers are in the high impedance state. this state is required for ydata input. when oel is low, the port is enabled for lsp output. oep 7 i p16-31/p0-15 output port three-state control. a low on this control line enables the output port. when oep is high, the output drivers are in the high impedance state. the following pin descriptions apply to the hmu16 only clkx 64 i x-register clock. the rising edge of this clock loads the x-data input register along with the tcx and rnd registers. clky 44 i y-register clock. the rising edge of this clock loads the y-data input register along with the tcy and rnd registers. clkm 8 i msp register clock. the rising edge of clkm loads the most significant product (msp) register. clkl 45 i lsp register clock. the rising edge of clkl loads the least significant product (lsp) register. the following pin descriptions apply to the hmu17 only clk 45 i clock. the rising edge of this clock will load all enabled registers. enx 64 i x-register enable. when enx is low, the x-register is enabled; x-input data and tcx will be latched at the rising edge of clk. when enx is high, the x-register is in a hold mode. eny 44 i y-register enable. eny enables the y-register. (see enx). enp 8 i product register enable. enp enables the product register. both the msp and lsp sections are enabled by enp. (see enx). hmu16, hmu17
5 functional description the hmu16/hmu17 are high speed 16 x 16-bit multipliers designed to perform very fast multiplication of two 16-bit binary numbers. the two 16-bit operands (x and y) may be independently speci?d as either two's complement or unsigned magnitude format by the two's complement controls (tcx and tcy). when either of these control lines is low, the respective operand is treated as an unsigned 16-bit value; and when it is high, the operand is treated as a signed value represented in two's complement format. the operands along with their respective controls are latched at the rising edge of the associated clock signal. the hmu16 accomplishes this through the use of independent clock inputs for each of the input registers (clkx and clky), while the hmu17 utilizes a single clock signal (clk) along with the x and y register enable inputs ( enx and eny). input controls are also provided for rounding and format adjustment of the 32-bit product. the round input (rnd) is provided to accommodate rounding of the most signi?ant portion of the product by adding one to the most signi?ant bit (msb) of the lsp register. the position of the msb is dependent on the state of the format adjust control (see pin descriptions and multiplier input/output format tables). the round input is latched into the rnd register whenever either of the input registers is clocked. the format adjust control ( f a) allows the product output to be formatted. when the f a control is high, a full 32-bit product is output; and when f a is low, a left-shifted 31-bit product is output with the sign bit replicated in bit position 15 of the lsp. the f a control must be high for unsigned magnitude, and mixed mode multiplication operations. it may be low for certain two's complement integer and fractional operations only (see multiplier input/ output formats table). the hmu16/hmu17 multipliers are equipped with two 16-bit output registers (msp and lsp) which are provided to hold the most and least signi?ant portions of the resultant product respectively. the hmu16 uses independent clocks (clkm and clkl) for latching the two output registers, while the hmu17 uses a single clock input (clk) along with the product latch enable ( enp). the msp and lsp registers may also be made transparent for asynchronous output through the use of the feed through control (ft). there are two output con?urations which may be selected when using the hmu16/hmu17 multipliers. the ?st con?uration allows the simultaneous access of the most and least signi?ant halves of the product. when the mspsel input is low, the most signi?ant product will be available at the dedicated output port (p16-31/p0-15). the least signi?ant product is simultaneously available at the bidirectional port shared with the y-inputs (y0-15/p0-15) through the use of the lsp output enable ( oel). the other output con?uration involves multiplexing the msp and lsp registers onto the dedicated output port through the use of the mspsel control. when the mspsel control is low, the most signi?ant product will be available at the dedicated output port; and when mspsel is high, the least signi?ant product will be available at this port. this con?uration allows access of the entire 32-bit product by a 16-bit wide system bus. hmu16, hmu17
6 hmu16, hmu17 multiplier input/output formats figure 1. fractional two? complement notation note: in this format an over?w occurs in the attempted multiplication of the two's complement number 1,000 . . . 0 with 1,000 . . . 0 yielding an erroneous product of -1 in the fraction case and -2 30 in the integer case. figure 2. fractional unsigned magnitude notation x 15 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 2 -15 2 -14 2 -13 2 -12 2 -11 2 -10 2 -9 2 -8 2 -7 2 -6 2 -5 2 -4 2 -3 2 -2 2 -1 -2 0 y 15 y 14 y 13 y 12 y 11 y 10 y 9 y 8 y 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 2 -15 2 -14 2 -13 2 -12 2 -11 2 -10 2 -9 2 -8 2 -7 2 -6 2 -5 2 -4 2 -3 2 -2 2 -1 -2 -0 p 31 p 30 p 29 p 28 p 27 p 26 p 25 p 24 p 23 p 22 p 21 p 20 p 19 p 18 p 17 p 16 2 -15 2 -14 2 -13 2 -12 2 -11 2 -10 2 -9 2 -8 2 -7 2 -6 2 -5 2 -4 2 -3 2 -2 2 -1 -2 0 p 15 p 14 p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 2 -30 2 -29 2 -28 2 -27 2 -26 2 -25 2 -24 2 -23 2 -22 2 -21 2 -20 2 -19 2 -18 2 -17 2 -16 -2 0 p 31 p 30 p 29 p 28 p 27 p 26 p 25 p 24 p 23 p 22 p 21 p 20 p 19 p 18 p 17 p 16 2 -14 2 -13 2 -12 2 -11 2 -10 2 -9 2 -8 2 -7 2 -6 2 -5 2 -4 2 -3 2 -2 2 -1 2 0 -2 1 p 15 p 14 p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 2 -30 2 -29 2 -28 2 -27 2 -26 2 -25 2 -24 2 -23 2 -22 2 -21 2 -20 2 -19 2 -18 2 -17 2 -16 2 -15 binary point x * = = msp msp signal digit value signal digit value lsp lsp signal digit value signal digit value fa = 0 fa = 1 x 15 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 2 -16 2 -15 2 -14 2 -13 2 -12 2 -11 2 -10 2 -9 2 -8 2 -7 2 -6 2 -5 2 -4 2 -3 2 -2 2 -1 y 15 y 14 y 13 y 12 y 11 y 10 y 9 y 8 y 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 2 -16 2 -15 2 -14 2 -13 2 -12 2 -11 2 -10 2 -9 2 -8 2 -7 2 -6 2 -5 2 -4 2 -3 2 -2 2 -1 p 31 p 30 p 29 p 28 p 27 p 26 p 25 p 24 p 23 p 22 p 21 p 20 p 19 p 18 p 17 p 16 2 -16 2 -15 2 -14 2 -13 2 -12 2 -11 2 -10 2 -9 2 -8 2 -7 2 -6 2 -5 2 -4 2 -3 2 -2 2 -1 p 15 p 14 p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 2 -32 2 -31 2 -30 2 -29 2 -28 2 -27 2 -26 2 -25 2 -24 2 -23 2 -22 2 -21 2 -20 2 -19 2 -18 2 -17 binary point x = msp signal digit value signal digit value lsp signal digit value fa = 1 mandatory
7 figure 3. fractional mixed mode notation figure 4. integer two? complement notation note: in this format an over?w occurs in the attempted multiplication of the two's complement number 1,000 . . . 0 with 1,000 . . . 0 yielding an erroneous product of -1 in the fraction case and -2 30 in the integer case. multiplier input/output formats (continued) x 15 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 2 -15 2 -14 2 -13 2 -12 2 -11 2 -10 2 -9 2 -8 2 -7 2 -6 2 -5 2 -4 2 -3 2 -2 2 -1 -2 0 y 15 y 14 y 13 y 12 y 11 y 10 y 9 y 8 y 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 2 -16 2 -15 2 -14 2 -13 2 -12 2 -11 2 -10 2 -9 2 -8 2 -7 2 -6 2 -5 2 -4 2 -3 2 -2 2 -1 p 31 p 30 p 29 p 28 p 27 p 26 p 25 p 24 p 23 p 22 p 21 p 20 p 19 p 18 p 17 p 16 2 -15 2 -14 2 -13 2 -12 2 -11 2 -10 2 -9 2 -8 2 -7 2 -6 2 -5 2 -4 2 -3 2 -2 2 -1 -2 0 p 15 p 14 p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 2 -31 2 -30 2 -29 2 -28 2 -27 2 -26 2 -25 2 -24 2 -23 2 -22 2 -21 2 -20 2 -19 2 -18 2 -17 2 -16 binary point x = msp signal (two? complement) digit value signal (unsigned magnitude) digit value lsp signal digit value fa = 1 mandatory x 15 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 -2 15 y 15 y 14 y 13 y 12 y 11 y 10 y 9 y 8 y 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 2 0 2 1 2 2 2 3 2 -4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 -2 15 p 31 p 30 p 29 p 28 p 27 p 26 p 25 p 24 p 23 p 22 p 21 p 20 p 19 p 18 p 17 p 16 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 2 28 2 29 -2 30 p 15 p 14 p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 -2 30 binary point x = msp signal lsp signal digit value fa = 0 digit value signal digit value p 31 p 30 p 29 p 28 p 27 p 26 p 25 p 24 p 23 p 22 p 21 p 20 p 19 p 18 p 17 p 16 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 2 28 2 29 2 30 -2 31 p 15 p 14 p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 signal digit value fa = 1 p 31 p 30 p 29 p 28 p 27 p 26 p 25 p 24 p 23 p 22 p 21 p 20 p 19 p 18 p 17 p 16 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 2 28 2 29 2 30 -2 31 p 15 p 14 p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 p 31 p 30 p 29 p 28 p 27 p 26 p 25 p 24 p 23 p 22 p 21 p 20 p 19 p 18 p 17 p 16 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 2 28 2 29 2 30 -2 31 p 15 p 14 p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 lsp msp hmu16, hmu17
8 figure 5. integer unsigned magnitude notation figure 6. integer mixed mode notation multiplier input/output formats (continued) x 15 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 y 15 y 14 y 13 y 12 y 11 y 10 y 9 y 8 y 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 binary point x = msp signal lsp signal digit value fa = 1 mandatory digit value signal digit value p 31 p 30 p 29 p 28 p 27 p 26 p 25 p 24 p 23 p 22 p 21 p 20 p 19 p 18 p 17 p 16 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 2 28 2 29 2 30 2 31 p 15 p 14 p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 x 15 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 -2 15 y 15 y 14 y 13 y 12 y 11 y 10 y 9 y 8 y 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 binary point x = msp signal (two? complement) lsp signal digit value fa = 1 mandatory digit value signal (unsigned magnitude) digit value p 31 p 30 p 29 p 28 p 27 p 26 p 25 p 24 p 23 p 22 p 21 p 20 p 19 p 18 p 17 p 16 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 2 28 2 29 2 30 -2 31 p 15 p 14 p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 hmu16, hmu17
9 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage applied . . . . . gnd 0.5v to v cc +0.5v storage temperature range . . . . . . . . . . . . . . . . . . . 65 o c to 150 o c operating conditions voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75v to +5.25v temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) plcc . . . . . . . . . . . . . . . . . . . . . . . . . . 43.2 15.1 cpga . . . . . . . . . . . . . . . . . . . . . . . . . . 42.69 10.0 maximum package power dissipation at 70 o c plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7w cpga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.46 maximum junction temperature plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 o c cpga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 o c maximum lead temperature (soldering, 10s). . . . . . . . . . . . .300 o c die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4500 gates caution: stresses above those listed in the ``absolute maximum ratings'' may cause permanent damage to the device. this is a stress only rating, and op eration at these or any other conditions above those indicated in the operations sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?ations v cc = 5.0v 5%, t a = 0 o c to 70 o c parameter symbol test conditions min max units logical one input voltage v ih v cc = 5.25v 2.0 - v logical zero input voltage v il v cc = 4.75v - 0.8 v output high voltage v oh i oh = 400ma, v cc = 4.75v 2.6 - v output low voltage v ol i ol = +4.0ma, v cc = 4.75v - 0.4 v input leakage current i i v i = v cc or gnd, v cc = 5.25v 10 10 a output or i/o leakage current i o v o = v cc or gnd, v cc = 5.25v 10 10 a standby power supply current i ccsb v i = v cc or gnd, v cc = 5.25v outputs open - 500 a operating power supply current i ccop v i = v cc or gnd, v cc = 5.25v f = 1mhz (note 2) - 7.0 ma note: 2. operating supply current is proportional to frequency, typical rating is 5ma/mhz. capacitance t a = 25 o c, note 3 parameter symbol test conditions typical units input capacitance c in frequency = 1mhz. all measurements referenced to device ground. 15 pf output capacitance c out 10 pf i/o capacitance c i/o 10 pf note: 3. not tested, but characterized at initial design and at major process/design changes. hmu16, hmu17
10 ac electrical speci?ations v cc = 5.0v 5%, t a = 0 o c to 70 o c, note 6 parameter symbol test conditions hmu16/hmu17-35 hmu16/hmu17-45 units min max min max unclocked multiply time t muc - 55 - 70 ns clocked multiply time t mc - 35 - 45 ns x, y, rnd setup time t s 15 - 18 - ns x, y, rnd hold time t h 2-2-ns clock pulse width high t pwh 10 - 15 - ns clock pulse width low t pwl 10 - 15 - ns mspsel to product out t pdsel - 22 - 25 ns output clock to p t pdp - 22 - 25 ns output clock to y t pdy - 22 - 25 ns three-state enable time t ena note 4 - 22 - 25 ns three-state disable time t dis - 22 - 25 ns clock enable setup time (hmu17 only) t se 15 - 15 - ns clock enable hold time (hmu17 only) t he 2-2-ns clock low hold time clkxy relative to clkml (hmu16 only) t hcl note 5 0 - 0 - ns output rise time t r from 0.8v to 2.0v - 8 - 8 ns output fall time t f from 2.0v to 0.8v - 8 - 8 ns notes: 4. transition is measured at 200mv from steady state voltage with loading specified in ac test circuit, v 1 = 1.5v, r 1 = 500 ? and c 1 = 40pf. 5. to ensure the correct product is entered in the output registers, new data may not be entered into the input registers before the output registers have been clocked. 6. refer to ac test circuit, with v 1 = 2.4v, r 1 = 500 ? and c 1 = 40pf. ac test circuit note: includes stray and jig capacitance. ac testing input, output waveforms note: ac testing: all parameters tested as per test circuit. input rise and fall times are driven at 1ns/v. dut c 1 (see note) v 1 r 1 0.3v 0v v oh v ol 1.5v 1.5v hmu16, hmu17
11 timing diagrams figure 7. setup and hold time figure 8. three-state control figure 9. hmu16 timing diagram figure 10. hmu17 timing diagram data input clock input 3.0v 1.5v 0v 3.0v 1.5v 0v t s t h three state control t dis t ena 1.5v output state high impedance three 1.3v 1.7v t pwh t hcl clkx clky t s t h input xi yi rnd clkm clkl output y mspsel output p t pwl t mc t pdy t pdsel t pdp t muc clk enx eny input xi yi rnd enp output y mspsel output p t pwh t se t he t pwl t s t h t se t he t pdy t pdsel t pdp t mc t muc hmu16, hmu17
12 hmu16, hmu17 ceramic pin grid array packages (cpga) index corner e1 e ? ? s d1 see note 9 c s s1 b b1 ? a e 0.008 c b b a see note 7 a l a1 q c 0.010 c a 0.030 b b l a1 q k seating plane at standoff d m m m m section b-b b2 section a-a g68.b mil-std-1835 cmga3-p68d (p-ac) 68 lead ceramic pin grid array package symbol inches millimeters notes min max min max a 0.215 0.345 5.46 8.76 - a1 0.070 0.145 1.78 3.68 3 b 0.016 0.0215 0.41 0.55 8 b1 0.016 0.020 0.41 0.51 - b2 0.042 0.058 1.07 1.47 4 c - 0.080 - 2.03 - d 1.140 1.180 28.96 29.97 - d1 1.000 bsc 25.4 bsc - e 1.140 1.180 28.96 29.97 - e1 1.000 bsc 25.4 bsc - e 0.100 bsc 2.54 bsc 6 k 0.008 ref 0.20 ref - l 0.120 0.140 3.05 3.56 - q1 0.025 0.060 0.64 1.52 5 s 0.000 bsc 0.00 bsc 10 s1 0.003 - 0.08 - - m11 111 n - 121 - 121 2 rev. 0 6/20/95 notes: 1. ??represents the maximum pin matrix size. 2. ? represents the maximum allowable number of pins. number of pins and location of pins within the matrix is shown on the pinout listing in this data sheet. 3. dimension ?1 includes the package body and lid for both cav- ity-up and cavity-down configurations. this package is cavity down. dimension ?1 does not include heatsinks or other attached features. 4. standoffs are required and shall be located on the pin matrix di- agonals. the seating plane is defined by the standoffs at dimen- sion ?1? 5. dimension ?1?applies to cavity-down configurations only. 6. all pins shall be on the 0.100 inch grid. 7. datum c is the plane of pin to package interface for both cavity up and down configurations. 8. pin diameter includes solder dip or custom finishes. pin tips shall have a radius or chamfer. 9. corner shape (chamfer, notch, radius, etc.) may vary from that shown on the drawing. the index corner shall be clearly unique. 10. dimension ??is measured with respect to datums a and b. 11. dimensioning and tolerancing per ansi y14.5m - 1982. 12. controlling dimension: inch.
13 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hmu16, hmu17 plastic leaded chip carrier packages (plcc) notes: 1. controlling dimension: inch. converted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ??is the number of terminal positions. -c- a1 a seating plane 0.020 (0.51) min view ? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ??typ. 0.004 (0.10) c -c- d2/e2 c l n68.95 (jedec ms-018ae issue a) 68 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.985 0.995 25.02 25.27 - d1 0.950 0.958 24.13 24.33 3 d2 0.441 0.469 11.21 11.91 4, 5 e 0.985 0.995 25.02 25.27 - e1 0.950 0.958 24.13 24.33 3 e2 0.441 0.469 11.21 11.91 4, 5 n68 686 rev. 2 11/97

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